The present invention relates to a method of fabricating an integrated circuit device. More particularly, the present invention relates to a method of forming recessed shallow trench isolation (STI) structures that is free of trench defects in the silicon substrate adjacent to the STI sidewalls.
Integrated circuits in microelectronic devices are becoming smaller in order to provide higher performance for products requiring advanced technology. The integrated circuits are comprised of several layers which are individually formed with a unique pattern. The pattern is transferred from a reticle or mask into a photoresist layer on a substrate during a lithography process. The pattern is then transferred from the photoresist layer into an underlying substrate by a plasma etch process. After the photoresist is removed, a pattern remains in the substrate and consists of trenches, via holes, or other features that form pathways for electrical connections within and between layers.
In certain layers, shallow trench isolation (STI) structures are needed to separate areas where active devices are to be located. The process typically involves forming a trench between areas where active devices will be located, filling the trench in a high density plasma (HDP) chemical vapor deposition (CVD) process with a dielectric material and employing a planarizing step such as chemical mechanical polishing (CMP) to smooth the surface. Dielectric materials such as silicon dioxide insulate active devices from one another and thereby prevent crosstalk between wiring which would have a detrimental impact on device performance. In advanced technologies, low k dielectric materials are being implemented because of their improved insulating capability.
Problems can occur when processing layers adjacent to an STI structure. U.S. Pat. No. 6,323,092 describes a method to prevent a recess from being formed in a dielectric material at the top corners of the STI structure during an etch to remove an overlying pad oxide. The recess causes an undesirable leakage current to be generated. An oxide is grown at the top corners of the STI structure to protect the dielectric material from an etchant.
An unwanted groove at the top corners of an STI structure is also addressed in U.S. Pat. No. 6,355,539. An oxide liner is formed in the trench before the dielectric material is deposited to fill the structure. Then a spacer consisting of layers of polysilicon and silicon dioxide is constructed adjacent to the trench. The spacer protects the STI corners during subsequent wet etch steps. The exposed silicon substrate and polysilicon in the spacer are oxidized to form a gate oxide layer and a continuous oxide spacer, respectively.
STI structures are modified to enable a larger process window when forming borderless contacts. In U.S. Pat. No. 6,133,105, a shallow trench contains two oxide layers separated by a nitride layer. The level of fill within the trench is recessed to allow a silicide spacer to be formed over an adjacent source/drain region and extend into the shallow trench. The silicide extension into the trench provides a better overlap when a hole to contact the silicide is printed slightly out of alignment. In a related patent, U.S. Pat. No. 6,303,465, the level of oxide within a shallow trench is recessed. A layer of conformal oxide is deposited followed by an etch stop layer such as silicon nitride. The nitride is etched back to protect the STI corners during subsequent processing.
In a flash memory process, the level of dielectric layer in an STI structure may be recessed below substrate level according to design. Furthermore, the level of dielectric layer in the trench in the cell array is usually lower than in the trench in the peripheral devices. As a result, exposed silicon in the substrate adjacent to the STI structures is especially susceptible to etching during subsequent process steps. For example, an STI structure is formed by a process that involves depositing a pad oxide on a substrate and a polysilicon layer on the pad oxide. A trench that is patterned in the polysilicon layer is etched through the pad oxide and into the substrate and is then filled with a dielectric material. After the dielectric layer is planarized and etched back to leave a recess within the trench, the polysilicon cap is typically removed by a plasma etch method. However, the exposed silicon substrate adjacent to the trench sidewalls is likely to be attacked by the etchant to form unwanted grooves adjacent to the STI structure. These grooves defects lead to a large cell leakage current that degrades device performance. Even in a rare situation when grooves are avoided during the polysilicon etch, the process window is so small as to not be acceptable for manufacturing requirements. Therefore, an improved method of forming a recessed dielectric layer within an STI structure without generating groove defects is needed. Ideally, the method should also encompass a large process window during the process of etching back the dielectric layer within the trench.
An objective of the present invention is to provide a method for forming a recessed dielectric layer in a STI structure such that no grooves or trenches are formed in the substrate adjacent to the STI structure.
Another objective of the present invention is to provide a low cost method for preventing trench defects in a substrate during fabrication of a recessed dielectric layer in a STI structure.
A still further objective is to improve the process window for etching a cap layer between trenches during the fabrication of recessed dielectric layer in a STI structure.
These objectives are accomplished by providing a substrate having a first dielectric layer such as a pad oxide formed thereon. A cap layer is deposited on the pad oxide layer and then trench openings are formed in the cap layer which is preferably polysilicon but may also be a hard mask such as silicon nitride. The trench pattern is transferred through the pad oxide and into the substrate with a plasma etch process. The width of the polysilicon and pad oxide is reduced by an etch step. A second dielectric layer is deposited to fill the trench openings and extends above the polysilicon layer. After a planarizing process to make the second dielectric layer coplanar with the polysilicon layer, an etch step is employed to recess the second dielectric layer in the trenches below the substrate surface. A buffer material such as high temperature oxide (HTO) is then deposited to form a conformal layer on the substrate. The buffer layer is etched back to expose the top surface of the polysilicon layer but remains on the sidewalls of the polysilicon layer an on the sidewalls of the trenches. A polysilicon etch can now be performed without causing any unwanted trenches in the substrate since the substrate adjacent to the STI structure is protected by a spacer comprised of the buffer material. Furthermore, the process window for the polysilicon etch is wide enough to be acceptable in a manufacturing scheme.